1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a semiconductor device having an MIS (metal insulator semiconductor) type field effect transistor and a method of manufacturing the same.
2. Description of the Prior Art
According to the recent miniaturization and high integration of the semiconductor device, thin film formation of a gate insulating layer has been accelerated. According to this tendency, reduction in a hot carrier resistance of the semiconductor device and a punch-through phenomenon of the impurity included in gate electrode constituting material to the substrate of the field effect transistor have become issues.
In general, a MIS field effect transistor, e.g., PMOS transistor is formed through manufacturing steps shown in FIGS. 1A to 1D.
At first, as shown in FIG. 1A, a field oxide layer (local oxidation of silicon:LOCOS) 102 is formed by selectively oxidizing a surface of a device isolating region of a silicon substrate 101. An n-type well 103 is then formed by introducing n-type impurity into a device forming region surrounded by LOCOS 102. An insulating layer 104 formed of SiO.sub.2 is formed by thermally oxidizing the device forming region on the surface of the silicon substrate 101.
Next, a polysilicon layer is formed on the insulating layer 104 and the field oxide layer 102. As shown in FIG. 1B, a gate electrode 105 is then formed by patterning the polysilicon layer by virtue of a photolithography technique.
Thereafter, a p-type impurity such as boron is introduced into the gate electrode 105 and the silicon substrate 1, so that conductivity of the gate electrode 105 can be made higher and impurity diffusion layers 106s, 106d of low impurity concentration are formed on both sides of the gate electrode 105.
Subsequently, as shown in FIG. 1C, dielectric side walls 107 are formed on side surfaces of the gate electrode 105. With the use of the gate electrode 105 and the side walls 107 as a mask, impurity diffusion layers 108s, 108d of high impurity concentration are then formed on both sides of the gate electrode 105. A source region 109s and a drain region 109d are formed to have a LDD (lightly doped drain) structure by the impurity diffusion layers 108s, 108d of high impurity concentration and the impurity diffusion layers 106s, 106d of low impurity concentration.
By the way, a thin silicon oxide layer is employed as material of the insulating layer 104 formed beneath the gate electrode 105. However, as shown in FIGS. 1B and 1D, if borons are ion-implanted as impurity into the silicon substrate 101, the impurity has punched through the gate electrode 105 and the insulating film 104 to thus lower n-type impurity concentration in the surface layer of the n-type well 103. As a result, a pn junction composed of the p-type impurity diffusion layers 106s, 106d of low concentration and the n-type well 103 occurs in an area substantially deeper than the surface of the substrate.
On the contrary, in the MOS transistor, further improvement of the hot carrier resistance of an insulating film formed on the surface of the substrate has been requested with the progress of miniaturization.
Under these circumstances, it has been reported that, with the use of a silicon oxynitride (SiON) layer as the insulating layer beneath the gate electrode, punch-through of boron ions to the semiconductor substrate beneath the gate electrode can be prevented by the silicon oxynitride layer. In addition, it has been reported that hot carrier resistance can be improved by forming a silicon oxynitride layer on source/drain regions of the semiconductor substrate.
In order to achieve two major objects of employing the silicon oxynitride layer simultaneously, the silicon oxynitride layer which is formed on a principal surface of the semiconductor substrate as the gate insulating layer has been used as it is as a covering film on the source/drain regions.
If the silicon oxynitride layer is formed on the drain region as the covering film, drain avalanche hot carrier resistance can be improved rather than the case where a thermally oxidizing silicon layer is formed as the covering film. Besides, if such effect would be enhanced, nitrogen concentration in the silicon oxynitride layer should be made higher.
If nitrogen is excessively included in the insulating layer beneath the gate electrode, the number of trapped hole or electron becomes large and also channel hot hole resistance or channel hot electron resistance is degraded.
If nitrogen is excessively included in the oxide film beneath the gate electrode, a threshold voltage in the transistor parameters is largely shifted to the negative direction rather than the case where no nitrogen is included.
Regarding such problem, it has been set forth in Patent Application Publication (KOKAI) 5-211330, for example, that, if nitrogen concentration of the silicon oxynitride layer in the source/drain regions of the field effect transistor is made higher than that of the silicon oxynitride layer beneath the gate electrode, hot carrier resistance can be improved and also a current driving factor can be enhanced by a low gate voltage.
However, unless nitrogen concentration in the insulating film formed immediately beneath the gate electrode is sufficiently high, punch-through of boron ions in the gate electrode and the insulating layer cannot be prevented. Therefore, it is not preferable that nitrogen concentration in the silicon oxynitride layer constituting the gate insulating layer is set lower than nitrogen concentration in the silicon oxynitride layer in the source/drain regions.
As stated above, in the MIS transistor technology in the prior art, there exists no structure which is able simultaneously to prevent the punch-through from the gate electrode to the silicon substrate, reduce a shift amount of the threshold voltage, improve the avalanche hot carrier resistance in the source/drain regions, and prevent degradation of the transistor parameters.